[Milkymist-devel] HDMI/DVI mixer extension for M1 - draft schematics
sebastien.bourdeauducq at lekernel.net
Wed Oct 10 13:02:10 PDT 2012
I've been working on a M1 daughterboard that can turn it into a simple
video mixer. It has two HDMI ports, one "crossfade" linear
potentiometer, and one "fade to black" knob.
Draft schematics are here:
Connection with the M1
Power and video streams are via the expansion port J21. The design is
compatible with all M1 revisions, including the very first six R1
prototypes. The two 5V pins that have been added in R2/R3 are not used,
instead, this voltage is supplied by the HDMI source.
I/Os are severely lacking on this port, thus:
1) TMDS needs to be converted to a single-ended I/O standard.
2) The HDMI HPD signal cannot be controlled.
3) The connection of the potentiometers is to be done using the M1's
memory card pins.
TMDS to LVCMOS conversion
Since there are no existing chips that can do this, we use a LVDS to
LVCMOS converter instead and tweak the voltage levels to make the
signals palatable to all devices involved.
TMDS requires a 50 ohm termination to 3.3V. It is not allowed to
terminate it to another DC voltage as it might cause some "monitor
detection" features to fail .
Since the encoding of the TMDS data makes the signal DC-balanced, we can
use a high-impedance AC coupling after the 50 ohm termination. The DC
bias to the 1.2V LVDS offset voltage is provided by a 8.2K/4.7K divider
connected to the 3.3V supply.
TMDS has up to 600mV single-ended swing , higher than the 400mV
maximum of LVDS. However, the MAX9121 chip can tolerate up to 1V. Using
a series resistor to reduce the swing as suggested in  would not have
been easily possible as the equivalent resistance of the divider network
is too high: the input capacitance of the chip combined with the high
series resistor value would quickly ruin the signal edges.
Now let's see if this works :)
Simple circuit here, the FPGA generates a rising edge on pin 4 and the
charge times of the capacitors through R59+P1/R60+P2 is measured after
thresholding by the Schmitt triggers U3/U4.
HDMI is characterized by massive and unpredictable clock skew, and
recovering the data requires a phase detector . Since the "hard"
phase detector can only be used with differential signals, we'll need to
reimplement it with 2X oversampling of the signal using ISERDES. This
oversampling can occur at a maximum of 945MHz due to the slowness of the
S6 I/O clocking, which will limit the pixel clock to 47.25MHz. A
resolution of 800x600 60Hz 24bpp should remain possible, however.
Another limitation is that, still due to the lack of I/O, the HPD signal
cannot be controlled. This can cause the video source to attempt DDC
transfers while the gateware is not ready, and finally give up and
disable the port. Connecting or enabling the video source only after the
M1 is ready should work reliably, though.
This add-on board should be good for prototyping HDMI and a simple video
mixer. Later, we may want to integrate those ports on the same board as
the FPGA, and get rid of the I/O hacks (which along with the improved
memory bandwidth in milkymist-ng should enable HD resolutions like 720p60).
 http://www.ddwg.org/lib/dvi_10.pdf p.36
 http://lekernel.net/diff_convert.pdf fig. 8
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