sebastien.bourdeauducq at lekernel.net
Fri Mar 26 06:05:32 PDT 2010
On Friday 26 March 2010 12:43:41 Adam Wang wrote:
> The new placement:
> 2, Fixed last  except J19. I'll get this sample next week to check.
Also check microSD card pinout:
If routing allows:
* in order to increase Flash bandwidth, connect D8-D15 to the FPGA (there must
be connected to special pins, indicated on the schematics symbol, because the
Flash is used for configuration). For 16-bit, the Flash's BYTE# pin must be
connected to 3.3V VCC (not FPGA's LDC or ground). See Xilinx UG380 p.48 .
If you switch the flash to 16-bit, addresses must be reorganized. The Flash's
A0 should be grounded (the flash datasheet says this pin becomes unused, but
it's safer to ground it than to leave it floating), FPGA's A0 should be
connected to Flash's A1, FPGA A1 -> Flash A2, etc. (see configuration waveform
on UG380 p.50).
Uwe: I checked, and Spartan-6 FPGAs do allow configuration in 16-bit mode
(they autodetect it using the first word which should always be the same in
* add an expansion header and route spare I/Os to it.
By the way, UG380 says that CCLK (Y21) requires termination (item 2 on p.48),
even if unused. p.47 says: "CCLK does not directly connect to parallel NOR
flash but is used internally to generate the address and sample read data."
So, please add the two resistors on the schematics, as described p. 52.
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