[Milkymist-devel] PCB layout instructions

[Adam Wang]

Hi,

> Here are the main points I'm thinking about. I may have written too much or
> too little - just tell me.

Always be the good things to write more.

> * Footprint review
> The PCB footprints need to be reviewed. Compare all data (pin numbers,
> geometries, plated/non-plated holes, ...) in the footprint libraries with the
> drawings in the datasheets.

I'm checking them. Will tell you soon.

> All datasheets can be found at:
> http://github.com/lekernel/milkymist-datasheets
> There should be only one discrepancy: I have numbered the pins of the DIN
> connectors according to the way they are numbered in MIDI rather than the way
> they are numbered in the datasheet. I have double-checked the current pinout
> and I strongly believe it to be correct.
> In case there is anything which is not 100% clear in the datasheet, I have
> samples of all the components in the BoM and I can make checks using them.

Could you send me a list of how many samples on hand?

> * DDR SDRAM layout
> A good document is available from Micron:
> http://download.micron.com/pdf/technotes/DDR/tn4614.pdf
> This document also recommends PCB layer stackups that we should use. I would
> choose the 4 signal layers option with 2 power planes.

Agreed on 6 layers.

> We'll use series terminations only with very short traces going to the FPGA.
> Do not spend too much effort on equalizing trace lengths. We have the FPGA's
> IODELAY elements to compensate for signal propagation delay discrepancies,
> and, contrary to length-equalizing (and length-increasing) zigzags, they do
> not cause additional signal integrity issues (ringing, noise, etc.).
> If you have time and an IBIS simulator, it would be a good idea to run a
> signal integrity simulation on the final routing.
> IBIS models for the FPGA's I/O cells can be downloaded from
> http://www.xilinx.com/support/download/sp6ibis.htm
> and those for the DRAM:
> http://download.micron.com/downloads/models/ibis/sdram/ddr/512meg/t37z_ibis.zip

I need to seek this for a while.
Well, you listed up a great summarization, I added others on [1].
Still working on this important stage before going for the placement.

[1] http://en.qi-hardware.com/wiki/Milkymist_One_Layout_Criteria

>
> * ESD protection
> As you may have noticed, there are several ESD protection cells made of a 1M
> resistor and a 4.7nF capacitor in parallel. You may want to cut the ground
> plane and add a little metal polygon under and around the concerned
> connectors, connected to their shells. Then place that ESD protection cells
> between the polygon and the ground plane.
> The Zener diodes near the DMX connectors are not meant to protect against ESD,
> but against clumsy users connecting microphone cables with 48V phantom power
> to the DMX plugs.
>
> * FPGA layout
> Layout guidelines (including instructions for the placement of the numerous
> decoupling capacitors) are documented in UG393, available from Xilinx or the
> datasheet repository.
>
> * FPGA pins assignment
> You can swap pins to make routing easier, but be careful of the special
> function pins (global clock capable pins, and pins that have a special
> behaviour during configuration). Most pins going to the Flash are not
> swappable because the Flash is used to configure the FPGA.
>
> * Ethernet routing
> There are some tips available at:
> http://pcb1001.blogspot.com/2009/07/ethernet-component-layout-guidelines.html
> We have integrated magnetics. These rules might be a little overkill, I know
> of several working Ethernet boards that do not respect them. In case of
> conflicts (for example, about board stackup), priority should be gived to
> notorious sources of problems like DDR SDRAM.
>
> * Global component/connector placement and board dimensions
> You are free to do whatever seems good. The current placement and dimensions
> are only indicative.
>
> * PCB constraints
> I'm thinking of 6 layers with 4 mil resolution (track width and clearance), 4
> mil annular rings, and 8 mil holes (yields a via outer diameter of 16 mil).
> You can of course discuss/improve this, but keep in mind that, for starters, a
> board with e.g. too many layers is better than no board at all because the
> project took too long to complete.
>
> * If you have ANY question, write me a mail.
>
> Thanks,
> Sébastien
>