[Milkymist-devel] DDR SDRAM layout considerations

[Uwe Bonnes]

Hello,

for some design, requiring big data pathes, I decided to go with the
XC6SLX45-FGG484, mostly for the number of available pins and ease of pin
assignment, as there are no input only pins as in XC3E. While first use will
be with an AVR Mikrocontroller and CAN controll access, it would come handy
to have at some point Linux and Ethernet on the board. So I decided to place
crucial Milkymist components on the board. Design is done with Eagle, and
design rules are 0.1mm lines/spaces, 0.2 mm minimum drill, as available as
option with MultiPCB with online calculator and with 6 layers.

I placed a lot of 0402 decoupling on the backside of the FPGA, local board
houses however still see some problems with glueing such small part but will
come back later...

Breakout of two banks of the FPGA is done (parallel flash with16 bit data,
mikrocontroller connections and big data pathes bus), with both banks nearly
fully occupied.  Now I am at the SDRAM bank. But I bang my head against the
Signal integry issues. With two SDRAM in TSOP66 package with 22.2 mm body
length, SDRAM trace length will reach 3 inches from FPGA to PAD, where
e.g. Micron TN4614.pdf starts to consider VTT termination. DQ0 Pin on RAM 1
and DQ7 on RAM2 are spaced about 30 mm apart, and without trace length
equalization this will cause about 150ps Skew. Using the DDR SDRAM 60 Ball
FBGA package could somehow relax trace length and matching requirments.
 
How will Milkymist1 tackle that issue?
- Can SDRAM access speed be sacrificed for relaxed timing margins requirements?
- Milkymist1 will not use VTT termination?
- Milkymist will not try to be compatible with the Spartan 6 Memory
controller?
- Will Milkymist1 use the DDR Ram in FBGA package?
- Any ideas for sensible DDR SDRAM routing?
- Does the HPDMC32 core place any special pin requirements on the pin usage?
- SDRAM_CK and SDRAM_CK_N are placed on GCLK pins in the milkymist One
draft, for any reason?
- Any other hints for me?

If anybody is interested in the Work-in-progress Eagle design files, please
let me know. The free version of Eagle should be able to view these files,
but not to change them.

Bye
-- 
Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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