[Milkymist-devel] Fwd: Re: VCOMP problem with blocking assignments

[Sébastien Bourdeauducq]

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Subject: Re: VCOMP problem with blocking assignments
Date: Tuesday 09 February 2010
From: Paul Campbell <paul at taniwha.com>
To: Sébastien Bourdeauducq <sebastien.bourdeauducq at lekernel.net>

On Tue, 09 Feb 2010, you wrote:
> Wow, that's wicked. I can hear the VHDL people laughing. Thanks for the 
heads-
> up, I will fix my code as you suggested.

heh - it's a historical thing I'm afraid and a little too subtle to be obvious 
which is why people get caught by it - the original verilog (pre-vhdl) was 
done by people who probably didn't understand a lot about computer languages 
but did understand hardware - that left us with a bunch of cruft that 
interpreted well but made writing compilers really hard. (I wrote the first 
version of this compiler prior to VCS).

When I started doing chip design (I have a background writing compilers) a lot 
of people still made assumptions about 0-time event ordering that had to do 
with virtually secret knowledge of how Verilog (the original simulator) did 
things (this particular issue with output regs is just such an area) - of 
course depending on any event ordering is just plain wrong - if you do you may 
well have something that mostly works

I've recently seen a bunch of low level hardware people who still think it's a 
good way to define an extracted latch is:

	assign q = (mux?in:q);

rather than including the delays they would need in the real world to make 
such a thing work reliably

	Paul

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