[Milkymist-devel] PCB-Layers and Design Rules for Milkymist hardware platform

[Sébastien Bourdeauducq]

On Thursday 29 October 2009 19:13:54 Uwe Bonnes wrote:
> Do you consider to use the raw MCB or MIG.

Raw MCB, as MIG uses some heavy Java-based graphical user interface that I do 
not like at all, and would not integrate well with the Milkymist design flow.

> If you use MIG, how to you plan to connect to the CPU. Via wishbone
> or direct?

Milkymist uses a custom pipelined and burst-oriented bus for DRAM access 
(called FML). Wishbone is inappropriate for accessing DRAM at high performance 
levels, because:
* It is not pipelined, so you have no effective means to hide the memory 
latency (except, to some extent, by implementing the arbiter in the 
controller, which is what a lot of designs do. But it makes the controller 
complex and not as efficient as HPDMC).
* Wishbone burst modes are complex and have many corner cases, making the DRAM 
controller into a huge bug-prone mess and wasting logic resources on features 
that are never used.

I have not looked yet at how the MCB could be connected to a FML interface. 
This would probably require some reverse engineering as Xilinx does not 
disclose any information about the MCB internals and says that you have to use 
it through MIG. They even encrypted the MCB simulation model using that 
ridiculous "SecureIP" mechanism similar to the Content Scramble System on DVD 
discs.

That's one of the reasons why I do not want to use the MCB right from the 
beginning, but I would like to keep this possibility open (without a PCB 
respin), just in case.

Sébastien