[Milkymist-devel] Memory test fail on ML-401

[Sébastien Bourdeauducq]

Hi,

On Saturday 18 July 2009 18.39.32 Clark Xin wrote:
> diff is attached, my current DQS value is 20.

I tried your patch on my board, and no DQS phase value worked anymore. This 
situation is really strange, because the DCM is supposed to cover the whole 
phase shift spectrum (0/360 degrees) when the DQS phase value goes from 0 to 
255. So any configuration should work.

So I was wondering if the DCM phase shift interface was properly set up. It 
turned out that using the "DCM" symbol for instantiation and "VARIABLE" as 
phase shift mode are not documented anywhere (but are still recognized by 
ISE?!). I changed them to "DCM_PS" and "VARIABLE_POSITIVE" according to the 
Virtex-4 primitive guide; and this made the DRAM work again.

But the phase value I'm now using is strange (244). This is supposed to mean 
that the DCM generates dqs_clk with a small shift *in advance* of sys_clk. But 
dqs_clk is supposed to be approx. 90 degrees *late* of sys_clk. WTF?!

Possible theories:
* DCM configuration is still not correct. Anyone understands how those pesky 
things work?
* Large clock skew due to routing delays (but you'd need a 2.5ns skew to 
explain this phenomenon, which is a lot)

If the new configuration with a 244 value still does not work on some boards, 
then a radical solution will be to let the BIOS calibrate automatically all 
timings at runtime. This will also solve the potential problem of variable 
clock skews when the design is modified because PAR can route the clock signal 
differently every time.

No wonder why Xilinx integrated a hard memory controller in their 6 series 
devices.

Sébastien