[Milkymist-devel] Memory test fail on ML-401

[Sébastien Bourdeauducq]

Hi,

On Saturday 18 July 2009 14.05.22 Clark Xin wrote:
> above DQS=129, random noise starts
> below DQS=29, random noise starts againg,
>
> from DQS=0 to DQS=~50 vertical patterns are getting less wider. but never
> the never vanishes.

Try adding a feedback loop to the clkgen_dqs DCM in boards/xilinx-
ml401/rtl/ddram.v.

Currently, ISE says:
WARNING:Timing:3158 - The DCM, clkgen_dqs, has the attribute CLK_FEEDBACK set 
to NONE. No phase relationship exists between the input and output clocks of 
this DCM. Data paths between these clock domains must be constrained using 
FROM/TO constraints.

You do need a phase relationship between input and output clocks of the DCM 
(that's what you're tuning using the calibration tool). While the current 
setup (which shows up this warning message) works perfectly on my board, it 
may be well possible that the generated clock phase is affected by 
temperature, silicon process variations and Murphy parameters.

See
http://www.xilinx.com/itp/xilinx6/books/data/docs/v4lsc/v4lsc0061_52.html

Also the Spartan-6 doc states clearly (and I guess it's the same for 
Virtex-4):
"CLK_FEEDBACK must be set to 1X or 2X to deskew CLK0. When CLK_FEEDBACK is set 
to NONE, no phase relationship with CLKIN is present."
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf p.33

Sébastien