[Milkymist-devel] Memory test fail on ML-401

[Clark Xin]

Hi,

I am using binaries of 2009-07-09 snapshot. It seems SDRAM test failed.
I tried to change input delay and DQS output phase with some random values
but no luck.
Log is below.

===============================================================
MILKYMIST(tm) BIOS    http://www.milkymist.org
(c) 2008, 2009 Sebastien Bourdeauducq

This program is free and excepted software; you can use it, redistribute it
and/or modify it under the terms of the Exception General Public License as
published by the Exception License Foundation; either version 2 of the
License, or (at your option) any later version.

I: BIOS CRC passed (33dbf7d4)
I: Running on Xilinx ML401 development board
I: Checking if SDRAM clocking is functional:
I:   PLL#1: Locked
I:   PLL#2: Locked
I: Initializing SDRAM [DDR200 CL=2 BL=8]...OK
I: SDRAM test...
E: Failed offset 0x00000000 (got 0x00000001, expected 0x00000000)
E: Aborted boot on memory error
BIOS> calibrate
================================
DDR SDRAM calibration tool
================================
Memo:
[> Input Delay
 r = reset to 0 taps
 u = add 1 tap
 d = remove 1 tap
[> DQS output phase
 U = increase phase
 D = decrease phase
[> Misc
 t = load image to framebuffer
 q = quit
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 060 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 061 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 062 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 063 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 064 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 065 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 066 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 067 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 068 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 069 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 070 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 071 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 072 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 073 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 074 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 075 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 076 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 077 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 078 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 079 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 080 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 081 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 082 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 083 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 084 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 085 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 086 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 087 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 088 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 089 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 090 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 091 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 092 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 093 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 094 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 095 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 096 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 097 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 098 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 099 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 100 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 101 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 102 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 103 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 104 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 105 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 106 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 107 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 108 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 109 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 110 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 111 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 112 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 113 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 114 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 115 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 116 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 117 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 118 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 119 (1/256 period)
Taps: 00 (78ps each) - DQS phase: 120 (1/256 period)

BIOS> memtest
I: SDRAM test...
E: Failed offset 0x00000000 (got 0x00000001, expected 0x00000000)
BIOS>
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