[Milkymist-devel] LatticeMico32 in TSMC 90nm

[Sébastien Bourdeauducq]

Hi,

Lately, I have had access to a computer with the Cadence RTL Compiler and the 
TSMC 90nm standard cell libraries to play with, so by curiosity I tried to run 
synthesis of the LatticeMico32 core.

The most interesting result is that it's RIDICULOUSLY FAST. It nearly meets 
timing at 800MHz, which is 7-8 times the speed on Virtex-4.
Power consumption is 29mW only at this frequency. Area is very small, with 
only 13K cells used (0.081 square millimeters).

If I did not do a mistake using the synthesizer (since it gets approximately 
the same number of flip-flops as in the FPGA implementation it's probably 
correct) and if these results are for real, they definitely make me want to 
leave FPGAs and do ASICs instead :)

The LM32 configuration is the same as the one used on ML401, except that I 
disabled the caches because the synthesizer apparently does not support RAM 
extraction and generated a mess of flip-flops instead.
Those results were obtained from the gate-level netlist only, with a wire load 
model. I did not try to lay out the core in silicon yet.

Attached are synthesis script + some reports from the tool.

Sébastien
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============================================================
  Generated by:           Encounter(R) RTL Compiler v07.10-s021_1
  Generated on:           Dec 15 2009  12:05:26 AM
  Module:                 lm32_top
  Technology library:     tcbn90gtc 110
  Operating conditions:   NCCOM (balanced_tree)
  Wireload mode:          segmented
============================================================

Instance  Cells  Cell Area  Net Area           Wireload             
--------------------------------------------------------------------
lm32_top  12554      81171         0  TSMC32K_Lowk_Conservative (S) 

 (S) = wireload was automatically selected
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============================================================
  Generated by:           Encounter(R) RTL Compiler v07.10-s021_1
  Generated on:           Dec 15 2009  12:05:27 AM
  Module:                 lm32_top
  Technology library:     tcbn90gtc 110
  Operating conditions:   NCCOM (balanced_tree)
  Wireload mode:          segmented
============================================================


 Clock Description
 ----------------- 

    Clock                              Clock    Source     No of   
    Name       Period  Rise   Fall     Domain  Pin/Port  Registers 
-------------------------------------------------------------------
 ideal_clock   1250.0   0.0   625.0   domain_1   clk_i        2135 

 Clock Network Latency / Setup Uncertainty
 ----------------------------------------- 

              Network   Network   Source   Source      Setup         Setup    
   Clock      Latency   Latency  Latency  Latency  Uncertainity  Uncertainity 
    Name       Rise      Fall      Rise     Fall       Rise          Fall     
------------------------------------------------------------------------------
ideal_clock       0.0       0.0      0.0      0.0           0.0           0.0 

 Clock Relationship (with uncertainity & latency)
 ----------------------------------------------- 

      From           To        R->R     R->F    F->R    F->F  
--------------------------------------------------------------
  ideal_clock   ideal_clock   1250.0   625.0   625.0   1250.0 
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  Generated by:           Encounter(R) RTL Compiler v07.10-s021_1
  Generated on:           Dec 15 2009  12:05:40 AM
  Module:                 lm32_top
  Technology library:     tcbn90gtc 110
  Operating conditions:   NCCOM (balanced_tree)
  Wireload mode:          segmented
============================================================

                 Leakage     Dynamic       Total    
Instance Cells  Power(nW)   Power(nW)    Power(nW)  
----------------------------------------------------
lm32_top 12554 171522.302 28388789.619 28560311.921 

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