[Milkymist-devel] Fwd: Case:C105969-072109 Title:Problems with lm32 SoC simulation with GDB.

[Sébastien Bourdeauducq]

Looks like we'd rather use the JTAG debugger than the instruction set 
simulator... This comes as little surprise as that simulator is so buggy that 
you cannot think they even tested it.

On the FPGA side, what we'd need to do is replace the Lattice primitives in 
the HDL code with Xilinx primitives (ie. BSCAN_VIRTEX4) with possibly some 
added glue logic. Another option is to implement the Lattice primitives using 
the regular FPGA resources (by implementing a synthesizable model of them), 
but then one would need to connect a second JTAG cable to the I/O connectors 
of the board.

On the software side, we can for example modify the Lattice software so that 
it can use the Platform Cable USB from Xilinx. Its protocol has been reverse 
engineered and is available in the UrJTAG source code.

There is an example of using the Platform Cable USB protocol and the 
BSCAN_VIRTEX4 primitive in the "ml401-flasher" directory in Milkymist SVN.

Sébastien



----------  Forwarded Message  ----------

Subject: Fwd: Case:C105969-072109 Title:Problems with lm32 SoC simulation with 
GDB.
Date: Tuesday 11 August 2009
From: Clark Xin <codinflu at gmail.com>
To: Sébastien Bourdeauducq <sebastien.bourdeauducq at lekernel.net>

---------- Forwarded message ----------
From: <techsupport at latticesemi.com>
Date: Sat, Aug 8, 2009 at 12:09 AM
Subject: Case:C105969-072109 Title:Problems with lm32 SoC simulation with
GDB.
To: codinflu at gmail.com



----- The following is an email from Lattice Semiconductor Corp.
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----- the keyword MESSAGE: below.
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Joe Maioriello
Applications Engineer,
Thank you.

CASE_ID_NUM: C105969-072109
CASE_TITLE: Problems with lm32 SoC simulation with GDB.
MESSAGE:

-----------------------------The message for you follows
-----------------------------

Hi Clark,

It appears that you are using a simulation methodology outside our normal
flow, and so your issues are unfamiliar to us.  I refer you to the Mico32
Software Refernece guide for instructions on doing an HDL simulation of the
Mico32 design and software.  That is typically how we simulate a Mico
system.  Most of the time we create the design, load it on an FPGA and debug
the code in real time via the debugger over the JTAG cable.

If you can provide more details on how you expect to use GDB to simulate
execution of code on a Mico system, maybe we can help, but since its outside
of the way we do things, it won't be given priority.

Thanks.

Joe



-- 
Regards
Clark

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